Index

Symbols

24x24 Device Pin Mapping CSV file

B

BRAM and DSP Inference

D

Design example Using FIFOs:

Design example Using SRAMs: Design flow

F

FIFO Features:

FIFO Usage:

G

Generate the ASCII header file format Generate the Binary file format

Generate the Jlink and OpenOCD file Generate the Programming files

H

Hardware Limitations and Online References

I

Installing Symbiflow on Linux

M

Macro Usage and examples:

Multiplier Features: Multiplier Usage:

O

Online References

P

PCF sample, [1] Performing Design Synthesis, [1] Performing the Post-Layout Simulation (verify the post layout verilog file) (verifying the configuration bits)

Performing the Pre-Layout Simulation, [1] Pin Mapping

R

RAM Features: RAM Usage:

Run design flow on a simple counter design (eos-s3) Running Pack, Place and Route Tools Running pack, Place and Route tools (eos-s3

S

S3B Device: Supported Commands, [1]

Symbiflow: Design flow (eos-s3) (qlf_k4n8/qlf_k6n10)