Supported Commands

Command option	Represented for (One with * supports only for qlf_k4n8)	Options
-synth	Synthesis using yosys	-
-compile	Run pack, place, route and generate fasm file	-
-src <source path>	Source file folder	-
-d <device>	Device supported	qlf_k4n8/qlf_k6n10
-P <package>	*Package csv file	qlf_k4n8 csv file
-p <pcf file>	*Fix Placement constraints of IO’s	-
-s <sdc file>	*Timing Constraint File (SDC)	Refer online documents section for SDC constraints supported
-r <router flag>	Timing: means no attention is paid to delay. Congestion: means nets on the critical path pay no attention to congestion	timing, congestion
-t <top module>	Top module of the Verilog design	-
-v <Verilog list files>	Verilog source files	Only Verilog supported
-pnr_corner	*Timing corner for the place and route tool	fast/slow
-analysis_corner	*SDF corner for the verilog post layout	fast/slow
-dump	Dump post layout verilog file	post_verilog

Below commands are supported only for synthesis(-synth option):

Command option	Represented for		Usage
-y	Specifies a verilog library directory to search for module definition. Multiple directories can be specified with space		-y <directory_path>
-f	Specifies a file that contains a list of commands to run		-f <filename>
+incdir+	Specifies the directories that contains the files declared with the `include compiler directive. Multiple directories can be specified with the + character		+incdir+<directory>
+libext+	Specify files with particular extension in the directory. You can specify more than one extension, separating each extension with the + character. Use this option when you enter the -y option		+libext+<extension>
+define+	Defines a text macro. Use `ifdef compiler directive in your Verilog source code		+define+<macro_name>=<value>