Run design flow on a simple counter design (EOS-S3)

Setup environment

To run any example, perform these steps once.

export INSTALL_DIR="specify the installpath"
#adding symbiflow toolchain binaries to PATH
export PATH="$INSTALL_DIR/quicklogic-arch-defs/bin:$INSTALL_DIR/quicklogic-arch-defs/bin/python:$PATH"
source "$INSTALL_DIR/conda/etc/profile.d/conda.sh"
conda activate

Entering an HDL Design:

1.Write a Verilog code for the design using any text editor.
2.Verify the syntax.
3.Create the simulation stimuli using any text editor.

The code and testbench for the example design are present at:
<Install_Path>/quicklogic-arch-defs/tests/counter_16bit/

• Performing the Pre-Layout Simulation
• Performing Design Synthesis
• Running pack, Place and Route tools (EOS-S3)
• Performing the Post-Layout Simulation (verifying the configuration bits)
• Performing the Post-Layout Timing Simulation
• Generate the Jlink and openOCD file
• Generate the ASCII header file format
• Generate the Binary File format
  • FPGA bin header
  • FPGA bitstream bin
  • FPGA meminit bin
  • FPGA iomux bin
• PCF Sample