Performing Design Synthesis

To perform a design synthesis:

In SymbiFlow, the synthesis of Verilog files is performed with Yosys. Yosys parses Verilog files, applies basic optimizations, performs technological mapping to FPGA blocks, and generates JSON and EBLIF files for the place and route tool.

Syntax:

ql_symbiflow -synth -src <source complete path> -d <device> -t <top module name> -v <verilog files>

cd <INSTALL_PATH>/quicklogic-arch-defs/tests/counter_16bit

and run the below command:

ql_symbiflow -synth -d ql-eos-s3 -t top -v counter_16bit.v

Output files for synthesis are:
<TOP>.eblif : netlist file for the design
<TOP>_synth.log : synthesis log information, refer this file for any issues during synthesis

Resource utilization in the top_synth.log of the counter:

Number of wires: 384
Number of wire bits: 384
Number of public wires: 382
Number of public wire bits: 382
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 67
BIDIR_CELL 18
CLOCK_CELL 1
C_FRAG 4
GMUX_IP 1
Q_FRAG 16
T_FRAG 27

Note

> All the output log files will be dumped in {source path}/build folder
> -src command is optional if run from the same directory where source files are present.