Generate the Jlink and openOCD file

JLINK file contains a script that can flash the board with the generated FPGA configuration via the JLink Connector

Syntax:

ql_symbiflow -compile -src <source complete path> -d <device> -t <top module name> -v <verilog files> -p <pcf file> -P <Package file> -s <SDC file> -dump jlink

The output files dumped will be:

<TOP>.jlink ->jlink file.

ql_symbiflow -compile -src $PWD -d ql-eos-s3 -t top -v counter_16bit.v -p chandalar.pcf -P PD64 -s counter_16bit.sdc -dump jlink

For details on how to configure the FPGA using the top.jlink file, refer to Download Binaries using Jlink SWD section in the QuickFeather_UserGuide pdf.

openOCD is an on-chip debugger file
Syntax:

ql_symbiflow -compile -src <source complete path> -d <device> -t <top module name> -v <verilog files> -p <pcf file> -P <Package file> -s <SDC file> -dump openocd

The output files dumped will be:

<TOP>.openocd ->openOCD file.

ql_symbiflow -compile -src $PWD -d ql-eos-s3 -t top -v counter_16bit.v -p chandalar.pcf -P PD64 -s counter_16bit.sdc -dump openocd