Performing the Post-Layout Timing Simulation

Post layout Timing simulation uses the SDF(Standard Delay Format) file.

The testbench for the counter design is present at:
<Install_Path>/quicklogic-arch-defs/share/symbiflow/tests/counter_16bit/

The post-layout design netlist is present at:
<Install_Path>/quicklogic-arch-defs/share/symbiflow/counter_16bit/build/top_post_synthesis.v

The SDF file is present at:
<Install_Path>/quicklogic-qrch-defs/share/symbiflow/counter_16bit/build/top_post_synthesis.sdf

The primitive file library file is present at:
<Install_Path>/quicklogic-arch-defs/share/symbiflow/techmaps/quicklogic/techmaps/<Family>/cells_sim.v

To perform a post-layout simulation:

- Perform a post-layout simulation of the Verilog code use iverilog.
- View the simulation results in the Waveform/ Data Analyzer and verify.

Note

> cells_sim.v : This file has the definition for technology mapped macros
> Supported only for QLF_K4N8