Performing Design Synthesis

To perform a design synthesis:

In SymbiFlow, the synthesis of Verilog files is performed with Yosys. Yosys parses Verilog files, applies basic optimizations, performs technological mapping to FPGA blocks, and generates JSON and EBLIF files for the place and route tool. Example is for qlf_k4n8.

Syntax:

ql_symbiflow -synth -src <source complete path> -d <device> -t <top module name> -v <verilog files>

cd <INSTALL_PATH>/quicklogic-arch-defs/share/symbiflow/tests/counter_16bit

and run the below command:

ql_symbiflow -synth -d qlf_k4n8 -t top -v counter_16bit.v

Output files for synthesis are present in ‘build’ folder:

<TOP>.eblif : netlist file for the design
<TOP>_synth.log : synthesis log information, refer this file for any issues during synthesis

Resource utilization in the top_synth.log of the counter:

Number of wires:                 23
Number of wire bits:             68
Number of public wires:          23
Number of public wire bits:      68
Number of memories:               0
Number of memory bits:            0
Number of processes:              0
Number of cells:                 48
  dff                            16
  lut                            16
  adder_lut4                     16

Note

> All the output log files will be dumped in {source path}/build folder
> -src command is optional if run from the same directory where source files are present.
> -synth option is supported for both devices QLF_K4N8 & QLF_K6N10.